While the scaling down of the device dimensions in a semiconductor integrated circuit continues, maintaining high drive current at scaled voltages and smaller gate dimensions becomes more important. Device drive current is closely related to gate length, gate capacitance, and carrier mobility. Different technology innovations have been made to address this issue. For example, strained silicon technology is demonstrated to boost carrier mobility in a MOS transistor without narrowing channel length. High-K (dielectric constant) gate dielectric is adopted to increase gate capacitance. A metal-gate electrode is used to increase gate capacitance and, therefore, increase the device drive current. A nonplanar device structure such as a FinFET transistor is developed to enable steeper channel-length scaling. Among these efforts, strained silicon technology has been demonstrated to significantly increase carrier mobility without adding much complexity into the existing manufacturing process.
With strained silicon technology, a silicon atom in a MOS transistor is displaced in its lattice. The displacement significantly reconfigures the energy band structure in the silicon to accelerate the flow of electrons and holes, thus increasing device drive current. Strain can be applied to a MOS transistor in different ways. One way to develop strain in a MOS transistor is by selectively forming an epitaxial layer of SiGe (silicon germanium) at the source/drain regions of a conventional MOS transistor. Because the lattice constant of the SiGe is larger than that of Si, the channel region between the two SiGe source/drain is placed under compressive stress. This device configuration enhances hole mobility in the channel region, thus increasing the drive current of a PMOS device. Conversely, a layer of silicon can be formed atop a relaxed SiGe layer. MOS transistors are then formed on the silicon layer. Due to the lattice constant mismatch between Si and SiGe, the Si layer is under constant biaxial, in-plane tensile strain. This device configuration has a benefit of enhancing the electron mobility in an NMOS device.
Strain can also be applied by forming a strained layer on a MOS transistor. The strained layer is also generally referred to as a strain-induced layer, stress layer, contact etching stop (CES) layer, or CES trained layer. In forming a CES layer, a silicon nitride film is deposited over a completed MOS transistor covering the source/drain regions, gate electrode and spacers. Because of the lattice spacing mismatch between the CES layer and underlying layer, an in-plane stress develops to match the spacing. A CES layer thus formed may exhibit different film stress over a broad range, from tensile to compressive, by controlling the N—H, Si—H and Si—N bond ratios in the CES layer and optimizing deposition conditions such as power, temperature and pressure in the processing chamber. It has been revealed that in-plane tensile stress in the channel region enhances electron mobility, thus increasing drive current in an NMOS device, and compressive stress parallel to channel length direction can enhance hole mobility, thus improving PMOS device performance.
FIG. 1 illustrates a strained NMOS and PMOS device of prior art formed in proximity on a silicon substrate 1. Shallow trench isolations (STI) 10 are formed in the silicon substrate 1 to isolate the NMOS device from the PMOS device. A tensile CES layer 14 formed atop the NMOS device introduces an in-plane tensile strain in the channel region 11, and therefore improves the drive current of the NMOS device. A compressive CES layer 16 formed atop the PMOS device introduces a compressive strain in the channel region 13, and therefore improves the drive current of the PMOS device. Although it is observed that the improvement on drive current is influenced by CES layer parameters such as the level of stress, the layer thickness, and the layer dimension. Little is revealed from prior art on how and in what manner these parameters affect the drive current in each type of MOS transistors. This situation has kept the current CES strained silicon technique more of a rule of thumb approach, where little can be done on device and process parameters to obtain an optimized increase on the device drive current. Moreover, in the prior art CES strained MOS transistors, the uniformity between enhanced MOS transistor drive currents is poor and scaled increase in drive current is difficult to achieve. This may result in detrimental effects in an integrated circuit such as skewed switching threshold, deteriorated noise margin, increased device time delay, and even a collapse of logic.
In view of these and other problems in the prior CES strain efforts to enhance carrier mobility and improve device performance, there is a need for a method of obtaining an optimized drive current increase with desired uniformity by fine tuning CES layer parameters in advanced MOS transistors.